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axi4_stream_source

clocked component

The STALL parameter randomly inserts idle cycles between beats (TVALID itself is never dropped mid-beat, as AXI4-Stream requires).

Parameters


STALL u64 optional 0..=255 weight for randomly gapping the stream between beats.

Ports


clk input clock Bus clock.
rst input reset Bus reset; drops in-flight beats and clears the queue.
axi modport $std::axi4_stream_if.transmitter

Methods


send(data: value)

Queues a beat (not the last of a packet).

send_last(data: value)

Queues the last beat of a packet (asserts TLAST).

random_traffic(count: u64, packet_len: u64)

Queues count random beats forming packets of about packet_len beats (a TLAST roughly every packet_len). Deterministic per seed.

idle() -> u64

1 when every queued beat has been accepted, else 0.

Usage


inst u0: $comp::axi4_stream_source (clk, rst, axi: );