axi4_stream_sink
clocked component
The STALL parameter randomly drops TREADY to backpressure the source.
Parameters
| STALL | u64 | optional | 0..=255 weight for randomly dropping TREADY; unset is always ready. |
|---|
Ports
| clk | input | clock | Bus clock. |
|---|---|---|---|
| rst | input | reset | Bus reset; clears the receive and expect queues. |
| axi | modport | $std::axi4_stream_if.receiver |
Methods
recv() -> value[axi.TDATA_WIDTH]
Pops the oldest received beat at full bus width, erroring if none.
expect(data: value)
Self-checks the next received beat against data; a mismatch fails
the test.
num_received() -> u64
Number of received beats not yet drained by recv.
beats() -> u64
Total beats accepted so far.
packets() -> u64
Total packets (TLAST beats) accepted so far.
idle() -> u64
1 when no self-check is still pending, else 0.
Usage
inst u0: $comp::axi4_stream_sink (clk, rst, axi: );