axi4_ram
clocked component
Burst-aware AXI4 slave memory. Connect to the slave modport. It accepts
INCR / FIXED / WRAP bursts, applies byte strobes per beat and echoes the
transaction ID. Up to MAX_OUTSTANDING reads run concurrently and their
beats are interleaved (out-of-order), so it stresses a master’s
reorder handling. It implements an exclusive-access monitor: an exclusive
read (ARLOCK) reserves its address, an exclusive write (AWLOCK) to a
still-reserved address succeeds with EXOKAY, and any intervening normal
write clears the reservation so the exclusive write fails with OKAY and
leaves memory untouched. Accesses past SIZE answer DECERR and set_resp
injects a per-address SLVERR/DECERR; errored writes leave memory
untouched. STALL backpressures the ready lines.
Parameters
| STALL | u64 | optional | 0..=255 weight for randomly dropping the ready outputs. |
|---|---|---|---|
| MAX_OUTSTANDING | u64 | optional | Concurrent reads (and buffered write responses); unset means 4. |
| SIZE | u64 | optional | Memory size in bytes; accesses at or above it answer DECERR. Unset means unbounded. |
Ports
| clk | input | clock | Bus clock. |
|---|---|---|---|
| rst | input | reset | Bus reset; clears in-flight bursts but keeps memory. |
| axi | modport | $std::axi4_if.slave |
Methods
poke(addr: u64, data: value)
Backdoor write of one aligned word at full bus width.
peek(addr: u64) -> value[axi.DATA_WIDTH_BYTES * 8]
Backdoor read of one aligned word at full bus width.
set_resp(addr: u64, code: u64)
Makes accesses to addr answer code (0 OKAY, 2 SLVERR, 3 DECERR);
OKAY clears any injected error. Errored writes do not modify memory.
fill(base: u64, count: u64)
Backdoor fill: sets count consecutive words starting at base to
their own address, so a master can predict read data without writing.
Usage
inst u0: $comp::axi4_ram (clk, rst, axi: );