axi4_lite_master
clocked component
expect_read/expect_write turn the master into a self-checking
scoreboard: it compares the read data (or checks the write response)
itself and fails the test on a mismatch. The STALL parameter randomly
delays READY to stress the slave.
Parameters
| STALL | u64 | optional | 0..=255 weight for randomly delaying BREADY/RREADY; unset never stalls. |
|---|---|---|---|
| MAX_OUTSTANDING | u64 | optional | Maximum responses in flight per direction; unset means unbounded. |
| W_DELAY | u64 | optional | Cycles to hold WVALID back after AWVALID, to skew the write address and data channels and stress the slave. Unset asserts them together. |
Ports
| clk | input | clock | Bus clock. |
|---|---|---|---|
| rst | input | reset | Bus reset; drops in-flight transactions and clears the queues. |
| axi | modport | $std::axi4_lite_if.master |
Methods
write(addr: u64, data: value)
Queues a full-width write.
write_strb(addr: u64, data: value, strb: value)
Queues a write with an explicit byte-strobe.
expect_write(addr: u64, data: value)
Queues a self-checking write: the response must be OKAY or the test fails.
read(addr: u64)
Queues a read; retrieve its data later with pop_read.
expect_read(addr: u64, data: value)
Queues a self-checking read: the returned data is compared against
data and a mismatch fails the test. No result is queued for
pop_read.
rmw(addr: u64, mask: value, value: value)
Queues an atomic read-modify-write: reads addr, replaces the bits
selected by mask with those from value, and writes it back. The
two accesses stay ordered on the bus by the hazard control.
random_writes(count: u64, addr_bits: u64)
Queues count self-checking writes of random data to random
word-aligned addresses within a 2^addr_bits-byte window, recording
each value. Drain them, then call verify_all to read them back and
check every location. Works at any bus width. Deterministic per seed.
random_strobed_writes(count: u64, addr_bits: u64)
Like random_writes but with a random partial byte-strobe on each
write, so partial-lane writes are exercised. The shadow copy is
merged byte-wise to match, then checked back by verify_all.
random_traffic(count: u64, addr_bits: u64, read_percent: u64)
Queues count random self-checking transactions to a
2^addr_bits-byte window, each a read with probability
read_percent/100 (checked against the value last written) or else a
write of random data. Same-address accesses are serialized on the bus
so reads always observe the intended value. Works at any bus width.
verify_all() -> u64
Queues a self-checking read of every address written by
random_writes, returning how many. Call after the writes have
drained; a read-back mismatch fails the test.
pop_read() -> value[axi.DATA_WIDTH_BYTES * 8]
Pops the oldest completed read at full bus width, erroring if none is ready.
num_reads() -> u64
Number of completed reads waiting in the result queue.
idle() -> u64
1 when every queued transaction has completed, else 0.
last_bresp() -> u64
Response code of the most recent write (0 = OKAY, 2 = SLVERR).
Usage
inst u0: $comp::axi4_lite_master (clk, rst, axi: );