clocked component
Passive AXI4-Lite protocol checker. Connect to the monitor modport;
it drives nothing and fails the test on any handshake or response
violation it sees. Works at any bus width (payloads compare as values).
TIMEOUT
u64 optional
Cycles a channel may stay stalled (VALID without READY) before it is
reported as a hang. Left unset the timeout is disabled.
LIVENESS
u64 optional
Cycles the bus may show no handshake at all while a response is
outstanding before it is reported as a deadlock. Unset disables it.
REPORT
str optional
If set, the end-of-test coverage summary is also written to this path.
clk
input clock Bus clock; every edge samples the monitored signals.
rst
input reset Bus reset; while asserted all VALIDs must stay low and handshake
history is cleared.
axi
modport $std::axi4_lite_if.monitor
inst u0: $comp::axi4_lite_checker (clk, rst, axi: );