axi3_master
clocked component
Active AXI3 master. Connect to the master modport. It issues up to
MAX_OUTSTANDING write bursts with distinct IDs and interleaves their W
beats by driving WID, exercising a slave’s write-data-interleaving path
(the AXI3-only feature dropped in AXI4). Reads pipeline out-of-order by ID
and are self-checked. exclusive_read / exclusive_write drive the 2-bit
AxLOCK and exclusive_ok reports the last exclusive write’s outcome.
Parameters
| STALL | u64 | optional | 0..=255 weight for randomly delaying BREADY/RREADY. |
|---|---|---|---|
| MAX_OUTSTANDING | u64 | optional | Maximum outstanding transactions per direction; unset means 4. |
Ports
| clk | input | clock | Bus clock. |
|---|---|---|---|
| rst | input | reset | Bus reset; drops in-flight bursts and clears the queues. |
| axi | modport | $std::axi3_if.master |
Methods
burst_write_fill(addr: u64, len: u64)
Queues a burst write whose beat values equal their addresses, recording
them for verify_all. Queue several to see their W data interleave.
random_burst_writes(count: u64, addr_bits: u64, max_len: u64)
Queues count random INCR burst writes (lengths up to max_len, capped
at the AXI3 16-beat limit) into a 2^addr_bits-byte window.
verify_all() -> u64
Queues a single-beat checked read of every written address. Returns how many; a read-back mismatch fails the test.
write(addr: u64, data: value)
Queues a single-beat normal write of data to addr.
read_burst(addr: u64, len: u64)
Queues an INCR burst read of len + 1 beats; drain with pop_read.
pop_read() -> value[axi.DATA_WIDTH_BYTES * 8]
Pops the oldest read beat at full bus width, erroring if none.
exclusive_read(addr: u64)
Queues a single-beat exclusive read of addr (2-bit ARLOCK = 0b01).
Its data drains through pop_read like any other read, sharing the same
FIFO — pop it before issuing later reads if you need the value.
exclusive_write(addr: u64, data: value)
Queues a single-beat exclusive write of data to addr (AWLOCK =
0b01); check the outcome with exclusive_ok once it has drained.
exclusive_ok() -> u64
1 if the most recent exclusive write got EXOKAY (succeeded), else 0.
idle() -> u64
1 when every queued and in-flight transaction has completed, else 0.
Usage
inst u0: $comp::axi3_master (clk, rst, axi: );