Verification IP for Veryl
Components
| axi3_checker |
Passive AXI3 protocol checker on the `monitor` modport. It enforces the |
| axi3_master |
Active AXI3 master. Connect to the `master` modport. It issues up to |
| axi3_ram |
AXI3 slave memory. Connect to the `slave` modport. Unlike AXI4 it accepts |
| axi4_checker |
Passive AXI4 protocol checker on the `monitor` modport. On top of the |
| axi4_lite_checker |
Passive AXI4-Lite protocol checker. Connect to the `monitor` modport; |
| axi4_lite_master |
`expect_read`/`expect_write` turn the master into a self-checking |
| axi4_lite_ram |
Backdoor `poke`/`peek`/`load_hex`/`set_resp` methods let a testbench |
| axi4_master |
Active AXI4 master. Connect to the `master` modport. Pipelines up to |
| axi4_ram |
Burst-aware AXI4 slave memory. Connect to the `slave` modport. It accepts |
| axi4_stream_checker |
Passive AXI4-Stream protocol checker. Connect to the `monitor` modport; |
| axi4_stream_sink |
The `STALL` parameter randomly drops `TREADY` to backpressure the source. |
| axi4_stream_source |
The `STALL` parameter randomly inserts idle cycles between beats (`TVALID` |