Veryl registryrggen/rggen-veryl-rtl · rggenSource ↗

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rggen_register_common

Parameters


Ports


READABLE bbool
WRITABLE bbool
ADDRESS_WIDTH u32
OFFSET_ADDRESS bit
BUS_WIDTH u32
DATA_WIDTH u32
VALUE_WIDTH u32
VALID_BITS bit
USE_ADDITIONAL_MATCH bbool
USE_ADDITIONAL_MASK bbool
i_clk input clock
i_rst input reset
register_if modport rggen_register_if register
i_additional_match input logic
i_additional_mask input logic
bit_field_if modport rggen_bit_field_if register