axi4_lite_ram
clocked component
Backdoor poke/peek/load_hex/set_resp methods let a testbench
preload memory, inspect it, and inject error responses in zero time.
Parameters
| READ_LATENCY | u64 | optional | Extra cycles before a read response. |
|---|---|---|---|
| WRITE_LATENCY | u64 | optional | Extra cycles before a write response. |
| STALL | u64 | optional | 0..=255 weight for randomly dropping READY; unset means never. |
| SIZE | u64 | optional | Memory size in bytes; accesses at or above it answer DECERR. Unset means unbounded. |
Ports
| clk | input | clock | Bus clock. |
|---|---|---|---|
| rst | input | reset | Bus reset; clears in-flight transactions but keeps memory contents. |
| axi | modport | $std::axi4_lite_if.slave |
Methods
poke(addr: u64, data: value)
Backdoor write of one aligned word at full bus width.
peek(addr: u64) -> value[axi.DATA_WIDTH_BYTES * 8]
Backdoor read of one aligned word at full bus width.
set_resp(addr: u64, code: u64)
Makes the slave answer a given address with a response code
(0 OKAY, 2 SLVERR, 3 DECERR). OKAY clears any injected error.
set_readonly(start: u64, len: u64)
Marks the [start, start + len) byte range write-protected: writes
there answer SLVERR while reads still succeed (models a ROM region).
dump_hex(path: str)
Writes the memory contents (the low 64 bits of each written word) out
as addr data hex pairs, sorted by address — the load_hex format.
load_hex(path: str)
Loads addr data hex pairs, one per line, into memory. Lines that
are blank or start with # are ignored.
Requires
| file |
|---|
Usage
inst u0: $comp::axi4_lite_ram (clk, rst, axi: );