axi3_ram
clocked component
AXI3 slave memory. Connect to the slave modport. Unlike AXI4 it accepts
interleaved write data: each W beat carries a WID that selects which
outstanding write burst it belongs to, so up to MAX_OUTSTANDING writes
can stream concurrently. It keeps an exclusive-access monitor (2-bit
AxLOCK, 0b01 = exclusive), interleaves reads out-of-order, and answers
DECERR past SIZE or an injected SLVERR/DECERR (set_resp).
Parameters
| STALL | u64 | optional | 0..=255 weight for randomly dropping the ready outputs. |
|---|---|---|---|
| MAX_OUTSTANDING | u64 | optional | Concurrent writes / reads / buffered responses; unset means 4. |
| SIZE | u64 | optional | Memory size in bytes; accesses at or above it answer DECERR. Unset means unbounded. |
Ports
| clk | input | clock | Bus clock. |
|---|---|---|---|
| rst | input | reset | Bus reset; clears in-flight bursts but keeps memory. |
| axi | modport | $std::axi3_if.slave |
Methods
poke(addr: u64, data: value)
Backdoor write of one aligned word at full bus width.
peek(addr: u64) -> value[axi.DATA_WIDTH_BYTES * 8]
Backdoor read of one aligned word at full bus width.
set_resp(addr: u64, code: u64)
Makes accesses to addr answer code (0 OKAY, 2 SLVERR, 3 DECERR);
OKAY clears any injected error. Errored writes do not modify memory.
Usage
inst u0: $comp::axi3_ram (clk, rst, axi: );