Veryl registryveryl-lang/vip · vipSource ↗

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axi3_checker

clocked component

Passive AXI3 protocol checker on the monitor modport. It enforces the per-channel handshake-stability rules and burst legality, counts WLAST per WID (write data may interleave), tracks B/R responses per ID (out of order), validates the 2-bit AxLOCK and that EXOKAY only answers an exclusive access, and reports coverage at $finish.

Parameters

TIMEOUT u64 optional Cycles a channel may stall without READY before a hang is reported.
REPORT str optional If set, the end-of-test coverage summary is written to this path.

Ports

clk input clock Bus clock.
rst input reset Bus reset; while asserted all VALIDs must stay low.
axi modport $std::axi3_if.monitor

Requires

file

Usage

inst u0: $comp::axi3_checker (clk, rst, axi: );