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rggen

Version 0.8.1
Repository https://github.com/rggen/rggen-veryl-rtl
License MIT

Modules

rggen_adapter_common
rggen_address_decoder
rggen_apb_adapter
rggen_apb_bridge
rggen_avalon_adapter
rggen_axi4lite_adapter
rggen_axi4lite_bridge
rggen_axi4lite_skid_buffer
rggen_bit_field
rggen_bit_field_counter
rggen_bit_field_w01trg
rggen_default_register
rggen_external_register
rggen_indirect_register
rggen_maskable_register
rggen_native_adapter
rggen_register_common
rggen_wishbone_adapter
rggen_wishbone_bridge

Interfaces

rggen_apb_if
rggen_avalon_if
rggen_axi4lite_if
rggen_bus_if
rggen_wishbone_if

Packages

rggen_rtl_pkg

Modules

rggen_adapter_common
rggen_address_decoder
rggen_apb_adapter
rggen_apb_bridge
rggen_avalon_adapter
rggen_axi4lite_adapter
rggen_axi4lite_bridge
rggen_axi4lite_skid_buffer
rggen_bit_field
rggen_bit_field_counter
rggen_bit_field_w01trg
rggen_default_register
rggen_external_register
rggen_indirect_register
rggen_maskable_register
rggen_native_adapter
rggen_register_common
rggen_wishbone_adapter
rggen_wishbone_bridge

rggen_adapter_common

Parameters

Ports

ADDRESS_WIDTH u32
LOCAL_ADDRESS_WIDTH u32
BUS_WIDTH u32
STROBE_WIDTH u32
REGISTERS u32
PRE_DECODE bbool
BASE_ADDRESS bit
BYTE_SIZE u32
USE_READ_STROBE bbool
ERROR_STATUS bbool
DEFAULT_READ_DATA bit
INSERT_SLICER bbool
i_clk input clock
i_rst input reset
bus_if modport rggen_bus_if slave
register_if modport rggen_register_if host [REGISTERS]

rggen_address_decoder

Parameters

Ports

READABLE bbool
WRITABLE bbool
ADDRESS_WIDTH u32
BUS_WIDTH u32
START_ADDRESS bit
BYTE_SIZE u32
USE_ADDITIONAL_MATCH bbool
i_address input logic
i_access input rggen_access
i_additional_match input logic
o_match output logic

rggen_apb_adapter

Parameters

Ports

ADDRESS_WIDTH u32
LOCAL_ADDRESS_WIDTH u32
BUS_WIDTH u32
REGISTERS u32
PRE_DECODE bbool
BASE_ADDRESS bit
BYTE_SIZE u32
ERROR_STATUS bbool
DEFAULT_READ_DATA bit
INSERT_SLICER bbool
i_clk input clock
i_rst input reset
apb_if modport rggen_apb_if slave
register_if modport rggen_register_if host [REGISTERS]

rggen_apb_bridge

Parameters

ADDRESS_WIDTH u32

Ports

i_clk input clock
i_rst input reset
bus_if modport rggen_bus_if slave
apb_if modport rggen_apb_if master

rggen_avalon_adapter

Parameters

Ports

ADDRESS_WIDTH u32
LOCAL_ADDRESS_WIDTH u32
BUS_WIDTH u32
REGISTERS u32
PRE_DECODE bbool
BASE_ADDRESS bit
BYTE_SIZE u32
ERROR_STATUS bbool
DEFAULT_READ_DATA bit
INSERT_SLICER bbool
i_clk input clock
i_rst input reset
avalon_if modport rggen_avalon_if agent
register_if modport rggen_register_if host [REGISTERS]

rggen_axi4lite_adapter

Parameters

Ports

ID_WIDTH u32
ADDRESS_WIDTH u32
LOCAL_ADDRESS_WIDTH u32
BUS_WIDTH u32
REGISTERS u32
PRE_DECODE bbool
BASE_ADDRESS bit
BYTE_SIZE u32
ERROR_STATUS bbool
DEFAULT_READ_DATA bit
INSERT_SLICER bbool
WRITE_FIRST bbool
i_clk input clock
i_rst input reset
axi4lite_if modport rggen_axi4lite_if slave
register_if modport rggen_register_if host [REGISTERS]

rggen_axi4lite_bridge

Parameters

ADDRESS_WIDTH u32

Ports

i_clk input clock
i_rst input reset
bus_if modport rggen_bus_if slave
axi4lite_if modport rggen_axi4lite_if master

rggen_axi4lite_skid_buffer

Parameters

ID_WIDTH u32
ADDRESS_WIDTH u32
BUS_WIDTH u32

Ports

i_clk input clock
i_rst input reset
slave_if modport rggen_axi4lite_if slave
master_if modport rggen_axi4lite_if master

rggen_bit_field

Parameters

Ports

WIDTH u32
INITIAL_VALUE bit
PRECEDENCE_ACCESS rggen_sw_hw_access
SW_READ_ACTION rggen_sw_action
SW_WRITE_ACTION rggen_sw_action
SW_WRITE_ONCE bbool
SW_WRITE_CONTROL bbool
SW_WRITE_ENABLE_POLARITY rggen_polarity
HW_WRITE bbool
HW_WRITE_ENABLE_POLARITY rggen_polarity
HW_SET bbool
HW_SET_WIDTH u32
HW_CLEAR bbool
HW_CLEAR_WIDTH u32
STORAGE bbool
EXTERNAL_READ_DATA bbool
EXTERNAL_MASK bbool
TRIGGER bbool
i_clk input clock
i_rst input reset
bit_field_if modport rggen_bit_field_if bit_field
o_write_trigger output logic
o_read_trigger output logic
i_sw_write_enable input logic
i_hw_write_enable input logic
i_hw_write_data input logic
i_hw_set input logic
i_hw_clear input logic
i_value input logic
i_mask input logic
o_value output logic
o_value_unmasked output logic

rggen_bit_field_counter

Parameters

Ports

WIDTH u32
INITIAL_VALUE bit
UP_WIDTH u32
DOWN_WIDTH u32
WRAP_AROUND bbool
USE_CLEAR bbool
i_clk input clock
i_rst input reset
bit_field_if modport rggen_bit_field_if bit_field
i_clear input logic
i_up input logic
i_down input logic
o_count output logic

rggen_bit_field_w01trg

Parameters

TRIGGER_VALUE bit
WIDTH u32

Ports

i_clk input clock
i_rst input reset
bit_field_if modport rggen_bit_field_if bit_field
i_value input logic
o_trigger output logic

rggen_default_register

Parameters

Ports

READABLE bbool
WRITABLE bbool
ADDRESS_WIDTH u32
OFFSET_ADDRESS bit
BUS_WIDTH u32
DATA_WIDTH u32
VALUE_WIDTH u32
VALID_BITS bit
i_clk input clock
i_rst input reset
register_if modport rggen_register_if register
bit_field_if modport rggen_bit_field_if register

rggen_external_register

Parameters

Ports

ADDRESS_WIDTH u32
BUS_WIDTH u32
VALUE_WIDTH u32
STROBE_WIDTH u32
START_ADDRESS bit
BYTE_SIZE u32
i_clk input clock
i_rst input reset
register_if modport rggen_register_if register
bus_if modport rggen_bus_if master

rggen_indirect_register

Parameters

Ports

READABLE bbool
WRITABLE bbool
ADDRESS_WIDTH u32
OFFSET_ADDRESS bit
BUS_WIDTH u32
DATA_WIDTH u32
VALUE_WIDTH u32
VALID_BITS bit
INDIRECT_MATCH_WIDTH u32
i_clk input clock
i_rst input reset
register_if modport rggen_register_if register
i_indirect_match input logic
bit_field_if modport rggen_bit_field_if register

rggen_maskable_register

Parameters

Ports

READABLE bbool
WRITABLE bbool
ADDRESS_WIDTH u32
OFFSET_ADDRESS bit
BUS_WIDTH u32
DATA_WIDTH u32
VALUE_WIDTH u32
VALID_BITS bit
i_clk input clock
i_rst input reset
register_if modport rggen_register_if register
bit_field_if modport rggen_bit_field_if register

rggen_native_adapter

Parameters

Ports

ADDRESS_WIDTH u32
LOCAL_ADDRESS_WIDTH u32
BUS_WIDTH u32
STROBE_WIDTH u32
REGISTERS u32
PRE_DECODE bbool
BASE_ADDRESS bit
BYTE_SIZE u32
USE_READ_STROBE bbool
ERROR_STATUS bbool
DEFAULT_READ_DATA bit
INSERT_SLICER bbool
i_clk input clock
i_rst input reset
csrbus_if modport rggen_bus_if slave
register_if modport rggen_register_if host [REGISTERS]

rggen_register_common

Parameters

Ports

READABLE bbool
WRITABLE bbool
ADDRESS_WIDTH u32
OFFSET_ADDRESS bit
BUS_WIDTH u32
DATA_WIDTH u32
VALUE_WIDTH u32
VALID_BITS bit
USE_ADDITIONAL_MATCH bbool
USE_ADDITIONAL_MASK bbool
i_clk input clock
i_rst input reset
register_if modport rggen_register_if register
i_additional_match input logic
i_additional_mask input logic
bit_field_if modport rggen_bit_field_if register

rggen_wishbone_adapter

Parameters

Ports

ADDRESS_WIDTH u32
LOCAL_ADDRESS_WIDTH u32
BUS_WIDTH u32
REGISTERS u32
PRE_DECODE bbool
BASE_ADDRESS bit
BYTE_SIZE u32
ERROR_STATUS bbool
DEFAULT_READ_DATA bit
INSERT_SLICER bbool
USE_STALL bbool
i_clk input clock
i_rst input reset
wishbone_if modport rggen_wishbone_if slave
register_if modport rggen_register_if host [REGISTERS]

rggen_wishbone_bridge

Parameters

ADDRESS_WIDTH u32
USE_STALL bbool

Ports

i_clk input clock
i_rst input reset
bus_if modport rggen_bus_if slave
wishbone_if modport rggen_wishbone_if master

Module Prototypes

Interfaces

rggen_apb_if
rggen_avalon_if
rggen_axi4lite_if
rggen_bus_if
rggen_wishbone_if

rggen_apb_if

Parameters

ADDRESS_WIDTH u32
BUS_WIDTH u32

rggen_avalon_if

Parameters

ADDRESS_WIDTH u32
BUS_WIDTH u32

rggen_axi4lite_if

Parameters

ID_WIDTH u32
ADDRESS_WIDTH u32
BUS_WIDTH u32

rggen_bus_if

Parameters

ADDRESS_WIDTH u32
BUS_WIDTH u32
STROBE_WIDTH u32

rggen_wishbone_if

Parameters

ADDRESS_WIDTH u32
BUS_WIDTH u32

Packages

rggen_rtl_pkg

rggen_rtl_pkg